Vivado vhdl half-adder

  • Vivado
  • VHDL
  • Xilinx

posted on 08 Feb 2017

Why build a half-adder?

There are many reasons, but I am doing this exercise as a reference design. A long time ago I did this exercise using Quartus II and ModelSim to target a Cyclone IV on a DE0-nano. Now I just want to make sure that I can do the same thing using Vivado to target my Zybo board.

Two half-adders can be combined to make full-adder. Adders are the building blocks of a computer’s ALU, and it recommend looking at this article for deeper conceptual understanding.

New Project

Create a new project and give it name that recognize. I will name this project ‘halfadder’, and store it in my default directory.

new-project

Click ‘Next’ to specify a project type. Choose ‘RTL Project’, and check the option to ‘Do not specify resources for this project’ because we are going to create our own sources for this project

rtl-project

Click ‘Next’ to specify the default part that we will targeting. Select ‘Boards’ and find your Zybo board (I get the files from Digilent’s GitHub repo).

zybo-board

Click ‘Next’ to see the Project Summary. Verify that it looks like this and then click ‘Finish’

project-summary

Click on ‘Add Sources’ in the Flow Navigator in the ‘Project Manager’ tree, and choose the ‘Add or Create Design Resources’ radio button on the next window.

add-sources

Click on the ‘Create File’ button to bring up a ‘Create Source File’ window. Ensure that File Type is VHDL. I am going to name this file ‘half_adder’.

file-naming

Click ‘Ok’ and then ‘Finish’ to bring up the ‘Define Module’ window. This window allows you the option to change the entity name and architecture names, but more importantly, the port definitions can be defined here. For a half-adder we should have two inputs (call them ‘a’ and ‘b’) and two outputs (‘sum’ and ‘carry’).

Now look at the Sources section and double-click on your half_adder.vhd file. We need to describe the circuit’s behavior so that ‘sum’ and ‘carry’ are defined in the architecture.

architecture Behavioral of half_adder is

begin
    sum <= a XOR b;
    carry <= a AND b;

end Behavioral

Save the file. We are going to add another source file which is the contraint xdc file that defines the physical pins of the Zybo board.